1. Field of the Invention
This invention relates generally to the field of memory systems, and more particularly, to the design of a memory controller.
2. Description of the Related Art
With present-day computer systems becoming increasingly more complex, and advances in technology leading to ever increasing processor speeds, it is becoming more and more difficult to optimize system performance, which oftentimes depends largely on the bandwidth and latency of the given system's memory. Consequently, accessing memory with the lowest latency, and highest use of memory bandwidth may improve and/or optimize the system's performance. As the required time to access the memory and complete a given memory request increases, the system slows down. Thus, any reduction in access time, and/or an overall increase in throughput on the memory bus may benefit system performance.
A large number of systems, including desktop computers, graphics adapter cards and notebook computers among others, use Dynamic random access memory (DRAM). DRAM devices provide many advantages over other memory technologies, including and most notably, static random access memory (SRAM) devices. The most important of these benefits are higher storage densities and less power consumption. However, these benefits come at the expense of various time delays incurred when preparing the memory cells and other components within DRAM devices for each subsequent access, for example before/after each read/write access. Examples of such delays include the time required to perform row precharge, row refresh, and row activation. In order to more precisely manage and control memory operations when incurring these delays, additional commands—which are transmitted between read/write accesses—have been created, resulting in additional overhead. A large percentage of DRAMs in use today belong to the double-data-rate synchronous DRAM (DDR SDRAM) family.
DDR SDRAM (including DDR2 and DDR3) achieves greater bandwidth than single-data-rate SDRAM by transferring data on the rising and falling edges of a strobe signal based on the system the clock. This effectively doubles the transfer rate, thereby improving system performance, without requiring an increase in the frequency of the memory bus. To further increase DRAM performance, the memory elements are oftentimes accessed in page configuration, in which a row of the DRAM may be active, or open (the row address strobe—RAS—signal does not need to remain asserted) while performing multiple reads or writes using separate column address strobe—CAS—signals. This allows successive reads or writes within the same row to avoid the delays usually associated with precharge and row access, and provides a noticeable increase in system performance during burst data transfers.
Typically, a memory page needs to be open before reads from the page or writes to the page can be performed. The DRAM controller may close the page immediately after a read/write command, or may decide to leave the page open. However, the limited capacity of the DRAM controller may preclude it from being able to handle many open pages. As a result, the DRAM controller may be required to close some of the open pages, even if leaving those pages open would eliminate some of the access delays during future transfers. Thus, limitations of the DRAM controller may present an obstacle to taking full advantage of operating a DRAM memory.
Other corresponding issues related to the prior art will become apparent to one skilled in the art after comparing such prior art with the present invention as described herein.